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| MOTOROLA Order Number: MC33989/D Rev. 4.1, 08/2001 Semiconductor Technical Data Advance Information System Basis Chip With High Speed CAN Transceiver The MC33989 is a monolithic integrated circuit combining many functions frequently used by automotive ECUs. It incorporates: - Two voltage regulators. - Four high voltage inputs. - 1Mbaud CAN physical interface. * Vdd1: Low drop voltage regulator, current limitation, over temperature detection, monitoring and reset function * Vdd1: Total current capability 200mA (including CAN current, 120mA for MCU and external peripheral components) * V2: control circuitry for external bipolar ballast transistor for high flexibility in choice of peripheral voltage and current supply. * Four operational modes (normal, stand-by, stop and sleep mode) * Low stand-by current consumption in stop and sleep modes * High speed 1MBaud CAN physical interface. * Four external high voltage wake-up inputs, associated with HS1 Vbat switch * 150mA output current capability for HS1 Vbat switch allowing drive of external switches pull up resistors or relays * Vsup failure detection * Nominal DC operating voltage from 5.5 to 27V, extended range down to 4.5V. * 40V maximum transient voltage * Programmable software time out and window watchdog * Safe mode with separate outputs for Watchdog time out and Reset * Wake up capabilities (four wake up inputs, programmable cyclic sense, forced wake up, CAN interface and SPI) * Interface with MCU through SPI MC33989 SYSTEM BASIS CHIP WITH HIGH SPEED CAN SEMICONDUCTOR TECHNICAL DATA DW SUFFIX PLASTIC PACKAGE CASE SO-28 PIN CONNECTIONS Simplified Block Diagram Q1 Vbat V2CTRL Vsup V2SENSE V2 R1 RX TX Vdd1 Reset INTB GND GND GND GND V2sense V2ctrl Vsup HS1 L0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vsup monitor Dual Voltage Regulator Vdd1 Monitor R2 5V/200mA Vdd1 5V/120mA Mode control HS1 control HS1 L0 L1 L2 L3 Oscillator Interrupt Watchdog Reset CAN supply INTB WDOGB WDOGB CSB MOSI MISO SCLK GND GND GND GND CANL CANH L3 L2 L1 Programmable wake-up input Reset MOSI SCLK MISO CSB Vdd1 TX RX Gnd ORDERING INFORMATION Device Operating Temperature Range Package (Top View) SPI Interface CAN H Rterm CAN L High Speed 1Mbit/s CAN Physical Interface None This document contains information on a new product. Specifications and information herein are subject to change without notice. TA = -40 to 125C SO-28 TM (c) Motorola, Inc., 2001. All rights reserved. MC33989 1 MAXIMUM RATINGS Ratings Symbol Min Typ Max Unit ELECTRICAL RATINGS Supply Voltage at Vsup - Continuous voltage - Transient voltage (Load dump) Logic Inputs (Rx, Tx, MOSI, MISO, CSB, SCLK, Reset, WDOGB, INTB) Output current Vdd1 HS1 - voltage - output current ESD voltage (HBM 100pF, 1.5k) - CANL, CANH, HS1, L0, L1, L2, L3 - All other pins ESD voltage (Machine Model) All pins L0, L1,L2, L3 - DC Input voltage - DC Input current - Transient input current (according to ISO7637 specification) and with external component tbd. THERMAL RATINGS V Vsup Vsup Vlog -0.3 27 40 Vdd1+0.3 V - 0.3 I Internally limited A V I Vesdh -0.3 Internally limited Vsup+0.3 V A kV -4 -2 Vesdm Vwu DC -0.3 -2 tbd 200 4 2 200 V 40 2 tbd V mA mA Junction Temperature Storage Temperature Ambient Temperature (for info only) Thermal resistance junction pin Tj Ts Ta Rthj/p - 40 - 55 - 40 +150 +165 +125 20 C C C C/W 2 System Basis Chip With High Speed CAN Transceiver MC33989 2 ELECTRICAL CHARACTERISTICS (Vsup From 5.5V to 18V and T j from -40C to 150C) For all pins except CANH, CANL, Tx and Rx which are described in the CAN module section Characteristics Description Vsup pin (Device power supply) Nominal DC Voltage range Extended DC Voltage range 1 Extended DC Voltage range 2 Input Voltage during Load Dump Input Voltage during jump start Supply Current in Stand-by Mode (note 2,4) Supply Current in Normal Mode (note 2) Supply Current in Sleep Mode (note 2,4) Vsup Symbol Min Typ Max Unit Conditions 5.5 4.5 18 18 5.5 27 40 27 15 15 45 65 V V V V V mA mA A Reduced functionality (note 1) (note 3) Load dump situation Jump start situation Iout at Vdd1 =10mA, CAN recessive state or disabled Iout at Vdd1 =10mA, CAN recessive state or disabled Vdd1 & V2 off, Vsup<12V, oscillator running (note5) CAN module disabled Vdd1 & V2 off, Vsup<12V oscillator not running (5) CAN module disabled, Vdd1 & V2 off, Vsup>12V oscillator running (5) CAN module disabled Vdd1 on, Vsup<12V oscillator running (5) CAN module disabled, Vdd1 on, Vsup<12V oscillator not running (5) CAN module disabled Vdd on, Vsup>12 oscillator running (5) CAN module disabled Vsup-ex1 Vsup-ex2 VsupLD VsupJS Isup(stdby) Isup(norm) Isup (sleep1) Supply Current in Sleep Mode (note 2,4) Isup (sleep2) Isup (sleep3) 25 40 A Supply current in sleep mode (note 2,4) 150 A Supply Current in Stop mode (note 2,4) I out Vdd1 <2mA Supply Current in Stop mode (note 2,4) Iout Vdd1 < 2mA Supply Current in Stop mode (note 2,4) Iout Vdd1 < 2mA Supply Fail Flag internal threshold Supply Fail Flag hysteresis Isup (stop1) Isup (stop2) Isup (stop3) Vthresh Vdet hyst 1.5 3 1 85 A 60 A 180 A 4 V V Note 1: Vdd1>4V, reset high, logic pin high level reduced, device is functional. Note 2: current measured at Vsup pin. Note 3: Device is fully functional. All functions are operating (All mode available and operating, Watchdog, HS1 turn ON turn OFF, CAN cell operating, L0 to L3 inputs operating, SPI read write operation). Over temperature may occur. Note 4: With CAN cell disabled. If CAN cell is enabled for wake up, an additional 100uA must be added to specified value. Note 5: Oscillator running means "Forced Wake up" or "Cyclic Sense" or "Software Watchdog in stop mode" timer activated. Oscillator not running means that "Forced Wake up" and "cyclic Sense" and "Software Watchdog in stop mode" are not activated. Vdd1 (external 5V output for MCU supply and internal CAN physical interface supply). Idd1 is the total regulator output current. Iddcan is the internal CAN block supply current. Iout is Vdd1 external output current. Idd1 = Iddcan + Iout. Vdd specification with external capacitor C>1uF and ESR<1O ohm. No tantalum capacitor required. Vdd1 Output Voltage Vdd1 Output Voltage Drop Voltage Vsup>Vddout Idd1 Current (Idd1 = Iddcan + Iout) Vdd1out Vdd1out Vdd1drop Idd1 200 4,9 4 0.2 270 0,5 350 5 5,1 V V V mA Idd1 from 2 to 200mA 5.5V< Vsup <27V Idd1 from 2 to 200mA 4.5V< Vsup <5.5V Idd1 = 200mA Internally limited Included Internal CAN current consumption Iout<=2mA Vdd1 Output Voltage in stop mode Thermal Shutdown Over temperature pre warning Vddstop Tsd Tpw 4,75 160 130 5,00 5,25 190 160 V C C VDDTEMP bit set System Basis Chip With High Speed CAN Transceiver 3 MC33989 (Vsup From 5.5V to 18V and T j from -40C to 150C) For all pins except CANH, CANL, Tx and Rx which are described in the CAN module section Characteristics Description Temperature Threshold difference Reset threshold 1 Reset threshold 2 Reset duration Vdd1 range for Reset Active Reset Delay Time Line Regulation Line Regulation Load Regulation Thermal stability Symbol Min Tsd-Tpw Rst-th1 Rst-th2 reset-dur Vddr td LR1 LR2 LD ThermS 20 4.3 3.6 1 1 5 5 10 20 5 20 25 25 50 4.5 V 3.8 Typ Max 40 4.7 4 2 ms V s mV mV mV mV 9V 4 System Basis Chip With High Speed CAN Transceiver MC33989 (Vsup From 5.5V to 18V and T j from -40C to 150C) For all pins except CANH, CANL, Tx and Rx which are described in the CAN module section Characteristics Description Rdson at Tj=25C, and Iout -150mA Rdson at Tj=150C, and Iout -150mA Rdson at Tj=150C, and Iout -120mA Output current limitation Over temperature Shutdown Leakage current Output Clamp Voltage at Iout= -10mA Cyclic sense period (refer to SPI) Cyclic sense On time (refer to SPI) Timing accuracy L0, L1, L2, L3 inputs Negative Switching Threshold Positive Switching Threshold Hysteresis Input current Wake up Filter Time DIGITAL INTERFACE TIMING SPI operation frequency SCLK Clock Period SCLK Clock High Time SCLK Clock Low Time Falling Edge of CS to Rising Edge of SCLK Falling Edge of SCLK to Rising Edge of CS MOSI to Falling Edge of SCLK Falling Edge of SCLK to MOSI MISO Rise Time (CL = 220pF) MISO Fall Time (CL = 220pF) Time from Falling or Rising Edges of CS to: - MISO Low Impedance - MISO High Impedance Time from Rising Edge of SCLK to MISO Data Valid Freq tpCLK twSCLKH twSCLKL tlead tlag tSISU tSIH trSO tfSO tSOEN tSODIS tvalid 250 125 125 100 100 40 40 50 50 25 25 25 25 50 50 50 50 50 4 MHz ns ns ns ns ns ns ns ns ns ns 0.2 V1SO 0.8V1, CL=200pF Vthn Vthp Vhyst Iin 2.5 tbd 3 tbd 0.7 tbd -10 8 20 3 3 3.7 3.7 3.5 tbd 4.5 tbd 1.3 tbd 10 38 V V V uA s 5.5V System Basis Chip With High Speed CAN Transceiver 5 MC33989 Figure 1. SPI Timing characteristics Tpclk CSB Tlead Twclkh Tlag SCLK Twclkl Tsisu Tsih MOSI Undefined Tvalid D0 Don't Care D8 Don't Care Tsodis Tsoen MISO D0 Don't Care D8 6 System Basis Chip With High Speed CAN Transceiver MC33989 3 CAN MODULE SPECIFICATION Ratings Symbol Min Typ Max Unit MAXIMUM RATING ELECTRICAL RATINGS CANL,CANH Continuous voltage CANH, CANL Transient voltage (Load dump, note1) CANH, CANL Transient voltage (note2) Logic Inputs (Tx, Rx) VcanH,L VtrH,L VtrH,L U -27 40 40 V V V V -40 - 0.5 40 6 ELECTRICAL CHARACTERISTICS VDD1 = 4,75 to 5,25; Vsup=5.5 to 27V; Tj = -40 to 150C unless otherwise specified Descriptions Supply Supply current of CAN cell Supply current of CAN cell Supply current of CAN cell (CAN cell in Sleep state) CANH and CANL Bus pins common mode voltage Differential input voltage VcanhVcanl Ires Idom Isleep Symbol Min Typ Max Unit Conditions 15 75 100 mA mA uA Recessive state Dominant state CAN cell in sleep state -2 7 500 V mV Recessive state at Rx Differential input voltage Differential input hysteresis (Rx) Input resistance Differential input resistance Unpowered node input current CANH output voltage CANL output voltage Differential output voltage CANH output voltage CANL output voltage Differential output voltage Output current at CANH Output current at CANL Over temperature shutdown TX and RX Tx Input High Voltage Tx Input Low Voltage Vih Vilp Icanh Icanl Tshut Rin Rind 900 100 5 10 100 100 1.5 2.75 0.5 1.5 4.5 2.25 3 3 2 100 -35 35 160 -100 150 mV mV Kohms Kohms mA V V V V V mV mA mA C Dominant state at Rx TX dominant state Tx dominant state Tx dominant state Tx recessive state Tx recessive state Tx recessive state Dominant state Dominant state 0.7 Vdd -0.4 Vdd+0.4 0.3 Vdd V V System Basis Chip With High Speed CAN Transceiver 7 Descriptions Tx High Level Input Current, Vtx=Vdd Tx Low Level Input Current, Vtx=0 Rx Output Voltage High, Irx=-250uA Rx Output Voltage Low, Irx=+1mA Timing Dominant State Timeout Propagation loop delay Tx to Rx Propagation delay Tx to CAN Propagation delay CAN to Rx Propagation loop delay Tx to Rx Propagation delay Tx to CAN Propagation delay CAN to Rx Symbol Iih Iil Voh Vol Min -10 -300 Vdd-1 Typ Max 10 -100 Unit uA uA V Conditions 0.5 V Tdout Tlrd Ttrd Trrd Tldr Ttdr Trdr 140 150 110 60 150 130 60 us ns ns ns ns ns ns note 1: Load dump test according to ISO7637 part 1 note 2: Transient test according to ISO7637 part 1, pulses 1,2,3a and 3b note 3: Human Body Model; C=100pF, R=1.5Kohms note 4: Machine Model; C=200pF, R=25ohms Figure 2. Transceiver AC characteristics Figure 3. Transceiver AC characteristics 8 System Basis Chip With High Speed CAN Transceiver MC33989 DEVICE DESCRIPTION 3.1 CAN error detection and wake up 3.1.1 Dominant State Time-out This protection is based on the fact that all CAN signals can not have more than five bits in a row with the same state. In case of a condition the Tx pin is stuck at 0v, the transceiver would hold the bus in dominant state making it impossible to the others CAN modules to use the bus. The protection acts releasing the bus when a dominant signal with more than 140uS is present in the Tx signal. After entering the fault condition the driver is disabled. To clear this disabled state the CAN transceiver needs to have its input going to recessive state. 3.1.2 Internal Error output flags There are internal error flags to signals when an error occurs. The flags are enabled when one of the below condition happens: * Thermal protection activated. * Over Current detection in CANL or CANH pins. * Time-out condition for dominant state. 3.1.3 Standby mode & Wake-up via CAN bus feature The HSCAN interface enters in a low consumption mode when the CAN standby mode s enable (stand-by mode). In this mode the HSCAN module will have a 100uA consumption via internal 5V. When in stand-by mode the transmitter and the normal receiver are disable, the only part of circuit which remains working is the wake up module. This module has a receiver to check the bus lines and according to its activity generate a wake up output signal. The conditions for the wake is meet when there are 3 valid pulses in a row. A valid signal must have a pulse width bigger than 0.5uS and no more than 0.5mS. diagram to be inserted Figure 4. Wake up block diagram The block diagram shows how the wake up signal is generated. First the CAN signal is detected by a low consumption receiver (WU receiver). The signal pass through a pulse width filter to validate the signal. The signal pass through a pulse width filter in order to select or discard the input signal according to its width. If the pulse width is greater than 500uS the signal pass to the "pulse ok" node with 0.5uS of delay. If the width of pulse is less than 0.5uS no signal appears on "pulse ok" node and a pulse appears in "Narrow pulse" node. A narrow pulse will reset the counter. The time-out generator block act as a retriggerable mono stable, when the first signal appears it causes a low signal output disabling the counter reset and beginning to count, if the next CAN signal do not occurs within 0.5mS the time out node will reset the counter. After the counter reach the number 3 the Wake up output is latched until the standby signal be disabled. The wake up output do not takes the CAN out of stand-by mode. In order to do this an external circuit should change the standby input signal. System Basis Chip With High Speed CAN Transceiver 9 MC33989 DEVICE DESCRIPTION 4 GENERAL DESCRIPTION The MC33989 is an integrated circuit dedicated to automotive applications. It includes the following functions: - One full protected voltage regulator with 200mA total output current capability. Available output current is 120mA at Vdd1 external pin. - Driver for external path transistor for V2 regulator function. - Reset, programmable watchdog function, INT, 4 operational modes - Programmable wake up input and cyclic sense wake up - Can high speed physical interface Device Supply The device is supplied from the battery line through the Vsup pin. An external diode is required to protect against negative transients and reverse battery. It can operate from 4.5V and under the jump start condition at 27V DC. This pin sustains standard automotive voltage conditions such as load dump at 40V. When Vsup falls below 3V typical the MC33989 detects it and store the information into the SPI register, in a bit called "BATFAIL". This detection is available in all operation modes. 4.2 Vdd1 Voltage Regulator Vdd1 Regulator is a 5V output voltage with output current capability up to 200mA. As the V1 regulator supplies the CAN module, 120mA is available at the Vdd1 external outside the circuit. This Vdd1 regulator is normally used in the application for the main microcontroller supply. It includes a voltage monitoring circuitry associated with a reset function. The Vdd1 regulator is fully protected against over current, short-circuit and has over temperature detection warning flags and over temperature shutdown with hysteresis. 4.3 V2 regulator V2 Regulator circuitry is designed to drive an external path transistor in order to increase output current flexibility. Two pins are used: V2 sense and V2 ctrl. Output voltage can be adjusted by an external resistor bridge, in a range from 1.8 to 8V. Vsup must be greater than V2 ctrl + 1V. Target ballast transistor is PNP MJD32C. Other PNP transistor might be used, however depending upon PNP gain an external resistor capacitor network might be connected between emitter and base of PNP. 4.4 HS1 Vbat Switch Output HS1 output is a 2 ohms typical switch from Vsup pin. It allows the supply of external switches and their associated pull up or pull down circuitry, in conjunction with the wake up input pins for example. Output current is limited to 200mA and HS1 is protected against short-circuit and over temperature. HS1 output is controlled from the internal register and SPI. It can be activated at regular intervals in sleep mode thanks to internal timer. It can also be permanently turned on in normal or stand-by modes to drive loads or supply peripheral components. No internal clamping protection circuit is implemented. Functional Modes The device has four modes of operation, the stand-by mode, normal mode, stop and sleep modes. All modes are controlled by the SPI. An additional temporary mode called "normal request mode" is automatically accessed by the device (refer to state machine) after wake up events. Two modes and configuration are possible for debug and program MCU flash memory. 4.5.1 Normal mode: In this mode both regulators are ON and this corresponds to the normal application operation. All functions are available in this mode (watchdog, wake up input reading through SPI, HS1 activation, CAN communication). The software watchdog is running and must be periodically cleared though SPI. 4.5.2 Standby mode: Only the regulator 1 is ON. Regulator 2 is turned OFF by disabling the V2 ctrl pin. Same functions as in normal mode are available. The watchdog is running. In this mode, the device supply current from Vbat can be as low as 500uA, in the case where the MCU is in power save mode and the CAN interface disabled. 4.5.3 Sleep mode: Regulators 1 and 2 are OFF. In this mode, the MCU is not powered. The sleep current from Vsup pin is less than 100uA (excluding CAN interface current). In this mode, the device can be awakened internally by cyclic sense via the wake up inputs pins and HS1 output, from the "forced wake up" function and from the CAN physical interface. 4.5.4 Stop mode Regulator 2 is turned OFF by disabling the V2 ctrl pin. The regulator 1 is activated in a special low power mode which allow to deliver 2 mA. The objective is to maintain the MCU of the application supplied while it is turned into power saving condition (i.e stop or wait mode). In the stop mode, the device supply current from Vbat can be as low as 100uA (excluding CAN interface current), in the case where the MCU is in power save mode and CAN interface disabled. Stop mode is entered through SPI. When the application is in stop mode (both MCU and SBC), the application can wake up from the SBC side (ex cyclic sense, forced wake up, CAN message, wake up inputs) or the MCU side (key wake up etc.). When Stop mode is selected by SPI, stop mode becomes active 20us after end of SPI message. The "go to stop" instruction must be the last instruction executed by the MCU before going to low power mode. 4.5 4.1 10 System Basis Chip With High Speed CAN Transceiver MC33989 In stop mode the Software watchdog can be "running" or "not running" depending upon selection by SPI. Refer to table 1 and SPI description. In stop mode, SBC wake up capability are identical as in sleep mode. refer to table 1. 4.5.4.1 Application wake up from SBC side: When application is in stop mode, it can wake up from the SBC side. When a wake up is detected by the SBC (ex CAN, Wake up input etc.) the SBC turns itself into Normal request mode. The wake up is signalled to the MCU through the INT pin. INT pin is pulled low for 10us and then returns high. Wake up event can be read through the SPI registers. 4.5.4.2 Application wake up from MCU side: When application is in stop mode, the wake up event may come to the MCU. In this case the MCU has to signal to the SBC that it has to go into Normal mod in order for the Vdd1 regulator to be able to deliver full current capability. This is done by a low to high transisiton of the CSB pin. CSB pin low to high activation has to be done as soon as possible after the MCU. Alternatively the L0 , L1, L2 and L3 inputs can also be used as wake up from stop mode. 4.5.4.3 Software watchdog in stop mode: If watchdog is enabled, the MCU has to wake up independently of the SBC before the end of the SBC watchdog time. In order to do this the MCU has to signals the wake to the SBC through the SPI wake up (CSB activation). Then the SBC wakes up and jump into the normal request mode. MCU has to configured the SBC to go to either normal or standby mode. The MCU can then decide to go back again to stop mode. If no MCU wakes up occurs within the watchdog timing, the SBC will activate the reset pin and jump into the normal request mode. The MCU can then be initialized. 4.5.5 Normal request mode: This is a temporary mode automatically accessed by the device after a wake up event from sleep or stop mode or after device power up. In this mode the Vdd1 regulator is ON, V2 is off, the reset pin is high. As soon as the device enters the normal request mode an internal 400ms timer is started. During these 400ms the micro controller of the application must addressed the SBC via SPI and configure the watchdog register. This is the condition for the SBC to stop the 400ms timer and to go into the Normal mode and to set the watchdog timer according to configuration. If no SPI configuration occurs within the 400ms, two cases must be considered: - The "BATFAIL flag" has not been cleared: in this case the SBC goes to reset mode for 1ms, then return to normal request mode. If no W/D configuration is done within 400ms, the SBC goes to reset again, then normal request etc. - If the "BATFAIL flag" has been reset, the SBC will goes back to previous low power mode. For instance If SBC was in sleep mode prior to the wake up it returns to sleep mode and keep the same wake up event configuration. If SBC was in stop mode, it return to stop mode and keep the same wake up event configuration. After an SBC power up (Vsup rising from zero to nominal), and if BATFAIL flag is cleared (MCR register read) the default low power mode is sleep mode. "BATFAIL flag" is a bit which is triggered when Vsup is below 3V. This bit is set into the MCR register. It is reset by MCR register read. 4.5.6 Reset and watchdog: mode1 and mode 2 (safe mode): The watchdog and reset functions have two modes of operation: mode 1 and mode 2 (mode 2 is also called safe mode). These modes are independent of the SBC modes (Normal, stand-by, sleep, stop). Mode 1 or mode 2 selection is done through SPI (register MCR, bit SAFE). Default mode after reset is mode 1. 4.6 4.7 Internal Clock The device has an internal clock used to generate all timings (reset, watchdog, cyclic wake up, filtering time etc....). Reset pin A reset output is available in order to reset the microcontroller. Two operation modes for the reset pin are available, mode 1 and mode 2 (refer to table for reset pin operation). The reset cause when SBC is in mode 1 are: - Vdd1 falling out of range: if Vdd1 falls below the reset threshold (parameter Rst-th), the reset pin is pull low until Vdd1 return to nominal voltage. - Power on reset: at device power on or at device wake up from sleep mode, the reset is maintained low until Vdd1 is within its operation range. - Watchdog time out: if the watchdog is not cleared the SBC will pull the reset pin low for the duration of the reset duration time (parameter: reset-dur). In mode 2, the reset pin is not activated in case of watchdog time out. Refer to" table for reset pin operation"for mode detail. For debug purposes at 25C, reset pin can be shorted to 5V. 4.8 Software watchdog (selectable window or time out watchdog) Software watchdog is used in the SBC normal and stand-by modes for the MCU monitoring. The watchdog can be either window or time out. This is selectable by SPI (register TIM1, bit WDW). Default is window watchdog. The period for the watchdog is selectable from SPI from 5 to 400ms (register TIM1, bits WDT0 and WDT1). When the window watchdog is selected, the closed window is the first half of the selected period, and the open window is the second half of the period. The System Basis Chip With High Speed CAN Transceiver 11 watchdog can only be cleared within the open window time. An attempt to clear the watchdog in the closed window will generate a reset. Watchdog is cleared through SPI by addressing the TIM1 register. Wake Up capabilities Several wake-up capabilities are available for the device when it is in sleep or stop mode. When a wake up has occurred, the wake up event is stored into the WUR or CAN registers. The MCU can then access to the wake up source. The wake up options are selectable trough SPI while the device is in normal or standby mode and prior to go to enter low power mode (sleep or stop mode). 4.9.1 Wake up from wake up inputs (L0, L1, L2, L3) without cyclic sense: The wake up lines are dedicated to sense external switches state and if changes occur to wake up the MCU (In sleep or stop modes). The wake up pins are able to handle 40V DC. The internal threshold is 3V typical and these inputs can be used as input port expander. The wake up inputs state can be read through SPI (register WUR). 4.9.2 Cyclic sense wake up (Cyclic sense timer and wake up inputs L0, L1, L2, L3) The SBC can wake up upon state change of one of the four wake up input lines (L0, L1, L2 and L3) while the external pull up or pull down resistor of the switches associated to the wake up input lines are biased with HS1 Vsup switch. The HS1 switch is activated in sleep or stop mode from an internal timer. Cyclic sense and Forced wake up are exclusive. If Cyclic Sense is enabled the forced up can not be enabled. 4.9.3 Forced wake up SBC can wake up automatically after a pre determined time spent in sleep or stop mode. Cyclic sense and Forced wake up are exclusive. If Forced wake up is enabled the Cyclic Sense can not be enabled. 4.9.4 CAN wake up The device can wake up from a CAN message if CAN wake up has been enabled. Refer to CAN module description for detail of wake up detection. 4.9.5 SPI wake up The device can wake up by the CSB pin in sleep or stop mode. Wake up is detetced by CSB pin transition from low to high level. In stop mode this correspond to the condition where MCU and SBC are in Stop mode and when the application wake up event comes through the MCU. 4.9.6 System power up At power up the device automatically wakes up. 4.10 SPI The complete device control as well as the status report is done through a 8 bits SPI interface. Refer to SPI paragraph. 4.11 CAN The device incorporates a high speed 1MBaud CAN physical interface. Its electrical parameters for the CANL, CANH, Rx and Tx pins are compatible to ISO11898 specification (IS0 11898: 1993(E)). The control of the CAN physical interface operation is done through the SPI interface. CAN modes are independant of the SBC operation modes. 4.12 Device power up After device or system power up the SBC enter into "normal request mode". 4.13 Package and thermal consideration The device is proposed in a standard surface mount SO28 package. In order to improve the thermal performances of the SO28 package, 8 pins are internally connected to the lead frame and are used for heat transfer to the printed circuit board. 4.14 Table 1: Reset and Wdogb operation. Mode1 and Mode2. Table below is the reset and watchdog output mode of operation. Two modes (mode 1 and mode 2) are available and are selectable through the SPI, safe bit. Default operation after reset or power up is mode 1. In both modes reset is active at device power up and wake up. In mode 1: Reset is activated in case of Vdd1 fall or watchdog not triggered. Wdogb output is active low as soon as reset goes low and stays low as long as the watchdog is not properly re-activated by SPI. In mode 2, safe mode: Reset in not activated in case of Watchdog failure. WDOGB output has same behavior as in mode 1. The Wdogb output pin is a push pull structure than can drive external component of the application in order for instance to signal MCU wrong operation. Even if it is internally turned on (low sate) the reset pins can be forced to 5V at 25C only, thanks to its internal limited current drive capability (capability used in Flash programming modes). 4.9 12 System Basis Chip With High Speed CAN Transceiver Events Device power up - Vdd1 normal - Watchdog properly triggered Vdd1 < Rst-th Watchdog time out reached - Vdd1 normal - Watchdog properly triggered Vdd1 < Rst-th Watchdog time out reached Mode 1 or 2 (safe mode) 1 1 1 2 (safe mode) 2 (safe mode) 2 (safe mode) WDOGB output low high high low (note1) high high low (note1) Reset output low to high high low low high low high note1: Wdogb stays low until the Watchdog register is properly addressed through SPI. Figure 5. Reset and Wdogb functions diagram in mode 1 and 2 Watchdog time out Vdd1 Reset MODE 1 WDOGB SPI W/D clear SPI CSB Watchdog register addressed Watchdog period MODE 2 Reset WDOGB 4.15 Application hardware and software debug with the SBC When the SBC is mounted on the same printed circuit board as the mico contoller it supplies, both application software and SBC dedicated rouitne must be debugged. Following features allow the user to debug the software by allowing the possiblity to disable the SBC internal software watchdog timer. 4.15.1 First SBC power up, reset pin connected to Vdd1 At SBC power up, the Vdd1 voltage is provided, but if no SPI communication occurs to configure the device in normal mode, a reset occurs every 400ms. In order to allow software debug and avoid MCU reset the Reset pin can be connected directly to Vdd1 by a jumper. 4.15.2 Debug modes with sowftare watchdog disabled though SPI (Debug Normal and Debug Standby) The software watchdog can be disabled through SPI. But in order to avoid unwanted watchdog disable and to limit the risk of disabling the watchdog during SBC normal operation the watchdog disable has to be done when the "bat fail flag" is set. The bat fail flag is set when the SBC supply voltage (Vsup) has been lower than 3V. This is the case at SBC power up. When this is done, the watchdog of the SBC is disabled, SBC can be used without having to clear the W/D on a regular basis to facilitate software and hardware debug. 4.15.3 MCU flash programming configuration In order to allow the possibility to download software into the application memory (MCU EEPROM or Flash) the SBC allows the following capabilities: The Vdd1 can be forced by an external power supply to 5V and the reset and Wdogb outputs by external signal sources to zero or 5V and this without damage. This allow for instance to supply the complete application board by external power supply and to apply the correct signal to reset pins. System Basis Chip With High Speed CAN Transceiver 13 5 TABLE OF OPERATION The table below describe the SBC operation modes. Voltage Regulator HS1 switch Vdd1: ON V2: OFF HS1: OFF Vdd1: ON V2: ON HS1 controllable Vdd1: ON V2: OFF HS1 controllable Vdd1: ON (2mA capability) V2: OFF HS1: OFF or cyclic Vdd1: OFF V2: OFF HS1 OFF or cyclic Vdd1: ON V2: ON HS1 controllable Vdd1: ON V2: OFF HS1 controllable Forced externally - CAN - SPI - L0,L1,L2,L3 - Cyclic sense - Forced Wake up - CAN - SPI - L0,L1,L2,L3 - Cyclic sense - Forced Wake up Wake up capabilities (if enabled) mode Reset pin INT Software Watchdog CAN cell Normal Request Low for 1ms, then high - Normally high. - Active low if W/D or Vdd1 under voltage occurs (and mode 1 selected) same as Normal Mode - Normally high. - Active low if W/D (*) or Vdd1 under voltage occurs (*): if enabled If enabled, signal failure (Vdd pre warning temp, CAN, HS1) same as Normal Mode Normal Running Tx/Rx Standby Running Tx/Rx Stop Signal SBC wake up (not maskable) - Running if enabled - Not Running if disabled - Low Power - Wake up capability if enabled - Low Power - Wake up capability if enabled same as Normal Sleep Low Not active No Running Debug Normal - Normally high. - Active low if Vdd1 under voltage occur - Normally high. - Active low if Vdd1 under voltage occur Same as Normal Not running Debug Standby Flash program ming Same as Standby Not running same as Standby not operating not operating not operating not operating Tableau 1 : table of operation "Debug Normal" and "Debug Standby" are entered vai SPI, register MCR. Bit BATFAIL must be set. Flash programming mode is a mode ,where the SBC outputs Vdd1, V2 and reset can be powered externaly to provide power to MCU and peripheral components. No function of the SBC are operating. Simplified connection used in Flash programming mode Vdd1 Vsup (0 or 12V) SBC reset Wdogb MCU = Flash Programming bus External supply and sources applied to Vdd1, reset and Wdogb test points on application circuit board. 14 System Basis Chip With High Speed CAN Transceiver 6 SIMPLIFIED STATE MACHINE Unpowered (Vsup =0) SBC power up, BATFAIL flag set (10) Vdd1 < Vdd reset & for t>100ms(8) No W/D config < 400ms & previous mode was sleep & BATFAIL bit previously read (BATFAIL reset) (11) No W/D config < 400ms & BATFAIL flag unread (not reset).(11) Normal request SBC wake up(1) Sleep - SBC Initialization - Reset low 1ms - Then reset high - Duration 400ms Vdd1 > Vdd reset and end of reset pulse SPI: - wake up config. - sleep W/D config < 400ms No W/D config < 400ms & previous mode was Stop & BATFAIL bit previously read (BATFAIL reset) (11) Vdd1 falls (3) or W/D failure (4) SPI: - standby mode & W/D config < 400ms Reset(9) SBC wake up (1)/ INT active, W/D timer stopped (node 5,6). SPI wake up (2,7) Normal SPI: - normal mode SPI: - wake up config. - W/D on or off - stop Vdd1 falls(3) or W/D failure (4) Vdd1 fall (3) or W/D time out (if enabled) Stop SPI: - wake up config - stop SPI: - wake up config - sleep Standby Comments: (1): SBC wake up: wake up from CAN, Lx, Cyclic sense or forced wake up. (2): SPI wake up: wake up from CSB pin (Wake up through MCU activity). (3): Vdd1 falls: Vdd1 falls below Vdd1 reset threshold (4): W/D failure: Watchdog not triggered before time out, or Watchdog trigger in the closed window. (5): In stop mode when SBC wakes up, wake up is transmitted to MCU through INT pin activation. INT stays low until INT register is read (cleared). (6): In stop mode, if W/D is enabled, when SBC goes out of stop mode before W/D time out, W/D timer is stopped. Then the normal request mode 400ms timer starts. If no SPI configuration occurs within the 400ms SBC goes back to Stop mode with same conditions (wake up, W/D enable etc.). (7): In stop mode when MCU goes out of its low power mode, this event is transmitted to SBC through an SPI wake up (CSB pin activation). (8): In case of short circuit or over load condition at Vdd. SBC goes to Sleep mode after 100ms. (9): In reset mode Vdd1 is ON and can deliver full current capability (120mA). Reset pulse occurs at reset pin. (10): BATFAIL bit is set to 1 when Vsup fall below 3V typical. (11): BATFAIL is reset when MCR register is read. System Basis Chip With High Speed CAN Transceiver 15 7 7.1 SPI INTERFACE AND REGISTER DESCRIPTION Data format description Bit7 MISO A2 Bit6 A1 Bit5 A0 Bit4 R/W Bit3 D3 Bit2 D2 Bit1 D1 Bit0 D0 MOSI Read operation: R/W bit = 0 Write operation: R/W bit = 1 address data The SPI is a 8 bit SPI. First 3 bits are used to identify the internal SBC register adress, bit 4 is a read/write bit. The last 4 bits are data send from MCU to SBC or read back from SBC to MCU. Following tables describe the SPI register list, and register bit meaning. Register containt at reset is also described. 7.2 List of Registers: Name MCR RCR CAN Adress $000 $001 $010 Description Mode control register Reset control register CAN control register Comment and usage Write: Control of normal, standby, sleep, stop, debug modes Read: BATFAIL flag and other status bits and flags Write: Configuration of reset voltage level and safe bit Write: CAN module control: Tx/Rx & sleep modes, slope control, wake enable/disable. Read: CAN wake up and CAN failure status bits Write: HS1 (high side switch) control in normal and standby mode Read: HS1 over temp bit Write: Control of wake up input polarity Read: Wake up input, and real time Lx input state Write: TIM1, Watchdog timing control, window or Timeout mode. Write: TIM2, Cyclic sense and force wake up timing selection Wrtite: HS1 periodic activation in sleep and stop modes, force wake up control. Write: Interrupt source configuration Read: INT source IOR WUR TIM LPC INTR Table 7-1. 7.2.1 $011 $100 $101 $110 $111 I/O control register Wake up input register Timing register Low power mode control register Interrupt register MCR register MCR W D3 WDSTOP BATFAIL 0 D2 MCTR2 VDDTEMP 0 D1 MCTR1 GFAIL 0 D0 MCTR0 WDRST 0 $000b R Reset Table 7-2. Control bits: BATFAIL X 0 0 X Table 7-3. 16 MCTR2 MCTR1 MCTR0 SBC mode Normal Request Normal Standby Stop Description automatically entered after reset 0 0 0 0 1 1 1 0 1 System Basis Chip With High Speed CAN Transceiver BATFAIL 0 1 (*) 1 (*) Table 7-3. MCTR2 1 1 1 MCTR1 0 0 1 MCTR0 0 1 0 SBC mode Sleep Normal Standby Description For debugging only, watchdog is disabled (*) : Bit BATFAIL cannot be set by SPI. BATFAIL is set when Vsup falls below 3V. WDSTOP 0 1 Status bits: Status bit GFAIL BATFAIL VDDTEMP WDRST 7.2.2 RCR register RCR W $001b R Reset Table 7-4. Control bits: D3 Watchdog in Stop mode OFF, watchdog not running once SBC is in Stop mode ON, watchdog running when SBC is in Stop mode Description Logic OR of CAN or HS1 failure Battery fail flag (set when Vsup < 3V) Temperature pre-warning on VDD (latched) Watchdog reset occurred D2 D1 SAFE D0 RSTTH 0 0 Condition Device power up V1 normal, WD is properly triggered V1 drops below 4.5 volt WD time out Table 7-5. SAFE 0 1 0 1 0 1 0 1 WDOGB pin 0 1 1 1 0 Reset pin 01 1 1 0 0 0 1 System Basis Chip With High Speed CAN Transceiver 17 RSTTH 0 1 Reset threshold voltage [V] 4.5 3.7 7.2.3 CAN register Description : control of the high speed CAN module, mode, slew rate and wake up CAN W $010b R Reset Table 7-6. 7.2.3.1 High speed CAN transceiver modes Description: Mode bit (D0) controls the state of the CAN module, Normal or Sleep mode. SCO bit (D1) defines the slew rate when the CAN module is in normal, and controls the wake up option (wake up enable or disable) when the CAN module is in sleep mode. CAN module modes (Normal and Sleep) are independant of the SBC modes. SC1 0 0 1 1 X X Status bits: Status bit CANWU TXF CUR THERM Description CAN wake-up occurred Permanent dominant TX CAN transceiver in current limitation CAN transceiver in thermal shut down SC0 0 1 0 1 1 0 MODE 0 0 0 0 1 1 CAN Mode CAN normal, slew rate 0 CAN normal, slew rate 0 Can normal, slew rate 0 Can normal, slew rate 0 Can sleep, wake up disable Can sleep, wake up enable CANWU TXF 0 CUR 0 THERM 0 D3 D2 SC1 D1 SC0 D0 MODE 7.2.4 IOR register Description.: control of HS1 in normal and standby modes IOR W $011b R Reset Table 7-1. HS1OT 0 D3 D2 HS1ON D1 D0 18 System Basis Chip With High Speed CAN Transceiver Control bits: HS1ON 0 1 Table 7-2. Status bits: Status bit HS1OT Description High side 1 over temperature HS1 state HS1 OFF, in normal and standby mode HS1 ON, in normal and standby mode Once the switch has been turned off because of over temperature, it can be turned on again by setting the appropriate control bit to "1". 7.2.5 WUR register The local wake-up inputs L0, L1, L2, and L3 can be used in both normal and standby mode as port expander and for waking up the SBC in sleep or stop mode. WUR W $100b R Reset Table 7-3. The wake-up inputs can be configured almost separetly, where L0 and L1 are configured toghether and L2 and L3 are configured toghether. Control bits:. LCTR3 X X X X 0 0 1 1 Table 7-4. LCTR2 X X X X 0 1 0 1 LCTR1 0 0 1 1 X X X X LCTR0 0 1 0 1 X X X X L0/L1 configuration inputs disabled high level sensitive low level sensitive both level sensitive inputs disabled high level sensitive low level sensitive both level sensitive L2/L3 configuration L3WU 0 L2WU 0 L1WU 0 L0WU 0 D3 LCTR3 D2 LCTR2 D1 LCTR1 D0 LCTR0 System Basis Chip With High Speed CAN Transceiver 19 Status bits: Status bit L3WU L2WU L1WU L0WU note : Status bits have two functions. After SBC wake up, they indicate the wake up source (LxWU set at 1 if wake up source is Lx). After SBC wake and once the WUR has been read, status bits indicates the real time state of the Lx inputs (1 mean Lx is above threshold, 0 means that Lx input is below threhold). 7.2.6 TIM registers Description : This register is splitted into 2 sub registers, TIM1 and TIM2. TIM1 controls the watchdog timing selection as well as the window or time out option. TIM1 is selected when bit D3 is 0. TIM2 is used to define the timing for the cyclic sense and forced wake up function. TIM2 is selected when bit D3 is 1. No read operation is allowed for registers TIM1 and TIM2 7.2.7 TIM1 register. TIM1 W $101b R Reset Table 7-5. Description WDW 0 0 0 0 1 1 1 1 Table 7-6. Watchdog operation (window and time out) window closed no watchdog clear allowed window open for watchdog clear window open for watchdog clear WDT1 0 0 1 1 0 0 1 1 WDT0 0 1 0 1 0 1 0 1 Watchdog timing [ms] 10 50 no window watchdog 100 400 10 50 100 400 window watchdog enabled (window lenght is half the watchdog timing) 0 0 0 D3 0 D2 WDW D1 WDT1 D0 WDT0 Wake-up occurred (sleep/ stop mode), logic state on Lx (standby/ normal mode) Description WD timing * 50% WD timing * 50% Watchdog period (WD timing selected by TIM 2, bit WDW=0) Time out watchdog Watchdog period (WD timing selected by TIM 2 bit WDW=1) Window watchdog 20 System Basis Chip With High Speed CAN Transceiver 7.2.8 TIM2 register The purpose of TIM2 register is to select an appropriate timing for sensing the wake-up circuitry or cyclically supplying devices by switching on or off HS1. TIM2 W $101b R Reset Table 7-7. 0 0 0 D3 1 D2 CSP2 D1 CSP1 D0 CSP0 CSP2 0 0 0 0 1 1 1 1 Table 7-8. CSP1 0 0 1 1 0 0 1 1 CSP0 0 1 0 1 0 1 0 1 Cyclic sense timing [ms] 5 10 20 40 75 100 200 400 Cyclic sense on time HS1 ON HS1 Cyclic sense timing, off time 100s HS1 OFF Lx sampling point sample t 7.2.9 LPC register Description: This register controls: - The state of HS1 in stop and sleep mode (HS1 permanently off or HS1 cyclic) - Enable or Disable the forced wake up function (SBC automatic wake up after time spend in sleep or stop mode, time defined by TIM2 register) - Enable of disable the sense of the wake up inputs (Lx) at sampling point of the cyclic sense period (LX2HS1 bit). LPC W $110b R Reset Table 7-9. D3 LX2HS1 D2 FWU D1 D0 HS1AUTO 1 0 0 0 System Basis Chip With High Speed CAN Transceiver 21 LX2HS1 X X 0 1 Table 7-10. HS1AUTO 0 1 X X Wake-up inputs supplied by HS1 Autotiming HS1 in sleep and stop modes off on, HS1 cyclic, perdio defined in TIM2 register no yes, Lx inputs sensed at sampling point 7.2.10 INTR register Description: This register allows to mask or enable the INT source. A read operation informs about the interrupt source. INTR W $111b R Reset Table 7-11. Control bits: Control bit CANF VDDTEMP HS1OT D3 D2 HS1OT HS1OT 0 D1 VDDTEMP VDDTEMP 0 D0 CANF CANF 0 Description Mask bit for CAN failures Mask bit for VDD medium temperature Mask bit for HS1 over temperature When the mask bit has been set, INTB pin goes low if the appropriate condition occurs. Status bits: Status bit CANF VDDTEMP HS1OT Description CAN failure VDD medium temperature (pre warning) HS1 over temperature 22 System Basis Chip With High Speed CAN Transceiver MC33989 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typical" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or un authorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the parts. Motorola and an Equal Employment Opportunity/Affirmative Action Employer. are registered trademarks of Motorola, Inc. Motorola, Inc. is MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other products or service names are the property of their respective owners. (c) Motorola, Inc. 2001. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 Technical Information Center: 1-800-521-6274 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu, Minato-ku, Tokyo 106-8573 Japan. 81-3-344-3569 ASIA / PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 HOME PAGE: http://www.motorola.com/semiconductors MC33989/D |
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